Synopsys Timing Constraints And Optimization User Guide 2021 !!exclusive!! May 2026

Introduction

• create_clock: Creates a clock constraint.
• set_input_delay: Sets the input delay constraint.
• set_output_delay: Sets the output delay constraint.
• set_max_delay: Sets the maximum delay constraint.
• dc_shell: Runs Synopsys Design Compiler.
• pt_shell: Runs Synopsys PrimeTime.
• hsim: Runs Synopsys Hsim.

Based on standard Synopsys documentation frameworks, the content is typically organized into the following functional sections: synopsys timing constraints and optimization user guide 2021

"When creating a generated clock using create_generated_clock, always specify the -source object as the master clock pin. In 2021, the -divide_by or -multiply_by options are recommended over -edges for simple frequency division to improve propagation accuracy. For non-integer division, use -edge_shift with care, as it may introduce glitches if the source clock edge alignment is not validated." The Synopsys Timing Constraints and Optimization User Guide